Wafer Level Chip Scale Packaging is different from the traditional chip package (Sawing before packaging and testing, and the volume will be increased at least 20% than the original chip). This latest technology is firstly film deposited on the wafer, then litho, electrochemical deposition, packaging and testing will be go on, at last been sawed into the same size die as the chip scale, without going through the wire and filling process, the chip size is almost the same as bare chip after packaging. Packaging efficiency close to 100%, in line with consumer electronics products’ market trend of light, small, short and thin, and has a large density, low induction, low cost, good heat dissipation and so on. The advantages of packaging are more obvious while wafer size increases and die size decreases.

     Application：

     IPD,PMU,Local Power，VCM Driver，Switch，Audio& Video，EEPROM,MEMS&Sensor，PA