NINGBO CHIPEX SEMICONDUCTOR CO.,LTD
Add:No.18 Zhongheng Road,Huaxing District,Andong Industrial Park,Hang Zhou Bay New Zone,Ningbo
P.O:315327
Mail:sales@chipex.cn
Tel:(86)-574-63078606;
(86)-574-63078608-8858
Copper pillar process is making copper-tin bumps on the surface of the chip for "point-of-connection" between the chips or the chips and the substrates by utilizing gluing, litho, electroplating and etching process and other production technology through the surface of the chip in the production of copper and tin bumps after wafer processing of the substrate circuit. The array of bumps on the die surface allows pin density to be higher due to the elimination of the traditional "wire bonding" to the surrounding metal, reducing the area of the chip to meet the performance requirements of the chip, low resistance, low parasitic capacitance, low inductance, low power consumption, low signal-to-noise ratio, low cost, and so on.
Cu-Pillar Structure | PI Thickness | Standard Cu-Pillar | Micro Cu-Pillar |
1M (Dirctl Cu-Pillar) | NA | Pitch:150um Bump Size:80-100um Bunp Height: 65um Cu+35um Sn | Min.Pitch:90um Min.Bump Size:45um Bum Hemp: 25um Cu+20um Sn |
1P1M (PI+Cu-Pillar) | 5um | ||
1P2M (PI+RDL+Cu-Pillar) | 5um | ||
2P2M 1st PI+RDL+2ndPI+Cu-Pillar | 1st PI5um 2ndPI 10um |
Application:
PMU.Smart.Card.RF.PA.MEMS&Sensor.ucontrollers.EEPROM/Dram/Flash/SRAM